Verilog/Design Questions (for beginners):-
Full case and Parallel case.
Swapping in two variables using blocking and non-blocking statement.
Hardware for below code, is there any problem with below codes.
begin begin
q1 = d; q3 = q2;
q2 = q1; q2 = q1;
q3 = q2; q1 = d;
end end
Hardware for 4-bit 2 input mux.
You have 9 inputs of 7-bit each, provided all inputs are equivalent except 1. Find the odd one.
Gray counter.
Asynch. and Synch. reset DFF code and hardware.
CaseX and CaseZ in verilog.
Difference between Blocking and Non-Blocking statements.
Difference between Mealy and Moore FSM.
Flop conversion.
Difference between Task and Function.
FIFO depth calculation, inputs given below:
Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s)
Outgoing Data= 8 DATA/10 Clock.
Burst size = 160
Realize below equation into Hardware structure:
A1 A0
x B1 B0
_______________
2-bit Full Adder hardware structure.
Implement basic gates using 2x1 Mux.
Implement Xor logic using NAND gate only.
Realize hardware for below piece of code:
input [1:0] sel; input [1:0]sel;
always @ (*) always @ (*)
begin begin
case(sel) case(sel)
2'b00 : out <= in1; 2'b00 : out <= in1;
2'b01 : out <= in2; 2'b01 : out <= in2;
2'b10 : out <= in3; 2'b10 : out <= in3;
endcase default: out <= 0;
end endcase
end
Difference between if-else and case statement, and hardware infer for them.
Difference between Latch and DFF, which is recommended to use and why.
What is timing loops and how to break them.
What is clock dividers.
