RTL_DESIGN_INTERVIEW_QUESTIONS

Verilog/Design Questions (for beginners):-

Full case and Parallel case.
Swapping in two variables using blocking and non-blocking statement.
Hardware for below code, is there any problem with below codes.
begin begin
q1 = d;          q3 = q2;
q2 = q1;       q2 = q1;
q3 = q2;       q1 = d;
end            end

Hardware for 4-bit 2 input mux.
You have 9 inputs of 7-bit each, provided all inputs are equivalent except 1. Find the odd one.
Gray counter.
Asynch. and Synch. reset DFF code and hardware.
CaseX and CaseZ in verilog.

Difference between Blocking and Non-Blocking statements.
Difference between Mealy and Moore FSM.
Flop conversion.
Difference between Task and Function.

FIFO depth calculation, inputs given below:
Writing Data = 80 DATA/100 Clock (Randomization of 20 Data’s)
Outgoing Data= 8 DATA/10 Clock.
Burst size = 160

Realize below equation into Hardware structure:
 A1 A0
      x B1 B0
 _______________

2-bit Full Adder hardware structure.
Implement basic gates using 2x1 Mux.
Implement Xor logic using NAND gate only.

Realize hardware for below piece of code:
input [1:0] sel;                                       input [1:0]sel;
always @ (*)                                         always @ (*) 
begin                                                      begin
case(sel)                                         case(sel)
2'b00 : out <= in1;                              2'b00 : out <= in1;
2'b01 : out <= in2;                              2'b01 : out <= in2;
2'b10 : out <= in3;                              2'b10 : out <= in3;
endcase                                               default: out <= 0;
end                                                              endcase
                                                                       end

Difference between if-else and case statement, and hardware infer for them.
Difference between Latch and DFF, which is recommended to use and why.
What is timing loops and how to break them.

What is clock dividers.

DIRECTIVES/CONSTRAINTS_FOR_CLOCK_DOMAIN_CROSSING_IN_VLSI

Directives/Constraints for CDC:

Following are some example of cdc directive commands:

• netlist clock — Identify clocks characteristics (including which clocks belong to the same clock groups).
netlist clock core_clk_a -period 10

• netlist port domain — Override the default clock groups assigned to DUT or instance ports.
netlist port domain input_port_in1 -clock core_clk_1

• netlist blackbox — Identify modules/architectures that should be treated as “black boxes” for CDC analysis.
netlist blackbox mem32_8

• netlist constant — Identify signals that should be considered constant for CDC analysis.
netlist constant test_sel 1'b0

• netlist memory — Identify large memories that are modeled as single sequential elements for CDC analysis.
netlist memory -module memory -abstract mem

• cdc preference — Set the preferences for static CDC analysis.
cdc preference -fifo_scheme -handshake_scheme

• cdc report scheme — Set severities for CDC schemes.
cdc report scheme port_combo_logic –severity caution

• cdc promote crossing and cdc promote scheme — Set promotion attributes for CDC crossings and schemes.
cdc promote crossing –promotion {off | on | protocol | fx} [–scheme scheme_name]

CLOCK_DOMAIN_CROSSING_IN_VLSI

CLOCK DOMAIN CROSSING:

Basic info about what it is:
As we well know that, with the time our design is getting shrink and getting complex as well. We will be having lots of clock domain* over a single small chip with huge and complex functionality. Each clock domains are having single or multiple clocks(generated clocks). Here, data transfers very frequently among these clock domains or we can say these clock domains are talking to each other. Therefore, CDC came into the picture to take care of the signals transceiving into one clock domain to another. Thus, helps to detect meta stability, data coherency etc. in order to avoid any functional issues.

Related terms to remember:

Clock Domain: A clock domain is a section of a design that operates on a clock, asynchronous to other clocks in the design.
For example: Domain "A" operates on clock_a  and Domain "B" operates on clock_b, provided clock_a and clock_b are asynchronous with each other.

Clock Dividers: If a clock (clka_1) which is generated (divided/multiplied) from another clock (clka), then clka_1 will be called as generated clock. Both belongs to same clock group and will be in sync. with each other.

Clock Group: All clocks which are part of the same clock domain builds a clock group. Hence, clock groups partition all of the clocks in the design. The clock groups identify the various clock domains in the design.

Asynchronous Clock: Any two clocks which don't have same clock frequency (or don't have constant relation in their clock frequency) or have same frequency but not same phase are asynchronous clocks.

Meta stability: Every Flop has its setup and hold requirements, if any signal violates either of them, flop output (response) will go hang between stable "1" and stable "0" value (we can't predict output value among 1 and 0). This phenomena is called as meta stability in the flop.

Synchronizer: It's a device which samples an asynch. signal and outputs a version of the same signal which has transitions synchronized to a local or sample clock (RX Clk).

HDM: Hierarchical data model, is a concise portable abstract model for capturing CDC intent of a block. Consists of info. like clock domain, generated clocks inside block, cdc related constraints, I/O ports etc. (Note: This  is specific to a company, could vary company to company.)

CDC analysis, There are two types of it:

1. Intra cdc analysis: Every IP owners has to perform cdc analysis on its IP and fix it at their level. Later they have to generate HDM file (encrypted file with extension .hierdb) of the same IP to deliver it for inter/soc level cdc analysis.

2. Inter cdc analysis: Once analysis is done at block level, by using all HDM files we will do cdc analysis at soc/top level. In this, tool will focus on HDM to HDM interface as well as their connection with the top level. This is assumed that, intra cdc analysis is been done before going for inter cdc analysis, to save our time and effort.

Tools available for CDC analysis:
Questa CDC ( 0-in ) Mentor Graphics
SpyGlass CDC Synopsys
Jasper CDC Cadence
etc.

CDC Techniques:
There are several techniques available for this, depending upon the type of signal crossing the boundary we use them.

1. From Slow to Fast Domain:
There is no such big issue if the signal is going from slow to fast domain. The only thing to check that the same signal could be sampled multiple times by the fast clock in RX domain. This could be taken care by using proper RTL code (using FSM style) such that same signal won't be sampled multiple times.
NOTE: There is no issue as long as fast clk(RX clk) is >= 1.5 slow clk(TX clk).

2. From Fast to Slow Domain:
Compare to above scenario, here we have to be more careful. Since, from fast to slow domain we could loss few data to sample in RX domain which is purely an issue. In fast domain, if one pulse is crossing cdc boundary and the same lies between two consecutive active edges of slow clock (RX CLK), it will be lost. Here, we have to use proper cdc technique to overcome this kind of problems.

Different CDC Techniques:
> For a single bit signal, we can use 2DFF synchronizer.
Purpose of using 2DFF is, we need to provide sufficient time to the signal crossing cdc boundary such that it can be sampled properly in RX domain. Here, 1st flop of synchronizer (B1) could undergo meta stability thus we are using 2nd flop (B2) with the intention that output of it will give us proper synchronized form of  TX signal (sig_1 in below figure).

                                                   TX Domain     |        RX Domain

                                           

> For passing a pulse from fast to slow domain, use toggle synchronizer.
Here, we require to stretch the pulse (sig_1) such that it can be sampled by the synchronizers in RX domain and for getting back the synchronized form of same pulse (sig_sync) do xoring of B2 and B3 outputs.

> For multibit transfer we can use re circulation mux technique, where we will take one cntl signal and will synchronize it in RX domain (by 2DFF in below figure). This synchronized cntl singal (B2>q) is then used as select signal for a mux residing in RX domain whose input is tied with the bus to get data from TX domain.

> If each bit of a bus is synchronized in RX domain using 2DFF separately, better to avoid skew effect and experience functional issue use grey encoding technique. Hence, only 1 bit is allowed to change at one time thus will avoid functional issue because of skew.

> For transferring vector data between two clock domains Asynchronous FIFO is called as safest technique. This will take care of all kinds of cdc issues.

There are few more techniques available like Hand shake(slow technique but more accuracy) etc.
Explore more.

Note: I'm sharing few pics below, will help you to understand cdc terms.

> Few cdc common scenarios given below with fixes.

> We can enable re-convergence check and its depth while running cdc.

> Few detail about HDM file and how to use them in cdc run with different switches.

Interview Questions:
1. What checks are required apart from cdc tech. while runing cdc?
2. What is CDC?

3. Why synchronizers are needed?

4. Different Synchronizer techniques?

5. How to synchronize a single bit signal?

6. How to synchronize a pulse?

7. If one IP is STA clean then do we need to do CDC on it?

8. What is pulse stretcher?

9. What if design is not CDC clean?

10. Why we do timing check on our design?

11. What is Re-convergence? Is it an issue, if yes solution for it?
12. What is Convergence and Divergence?
13. Why Reset synchronizer needed?

14. Constraints for cdc? 

Please comment back if I missed something.

*Suggestions are welcome*

Share this with others, since this is only for knowledge sharing purpose.

*Please find the below link for cdc related directives/constraints*
https://arvindece90.blogspot.com/2020/03/directivesconstraintsforclockdomaincros.html


Doc by: Arvind Singh
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